A computer system may be divided into three basic blocks: a central processing unit (CPU), memory, and input/output (I/O) units. These blocks are coupled to each other by a bus. An input device, such as a keyboard, mouse, stylus, analog-to-digital converter, etc., is used to input instructions and data into the computer system via an I/O unit. These instructions and data can be stored in memory. The CPU receives the data stored in the memory and processes the data as directed by a set of instructions. The results can be stored back into memory or outputted via the I/O unit to an output device, such as a printer, cathode-ray tube (CRT) display, digital-to-analog converter, etc.
The CPU receives data from memory as a result of performing load operations. Each load operation is typically initiated in response to a load instruction. The load instruction specifies an address to the location in memory at which the desired data is stored. The load instruction also usually specifies the amount of data that is desired. Using the address and the amount of data specified, the memory may be accessed and the desired data obtained.
Some computer systems have the capabilities to execute instructions out-of-order. In other words, the CPU in the computer system is capable of executing one instruction before a previously issued instruction. This out-of-order execution is permitted because there was no dependency between the two instructions. That is, the subsequently issued instruction does not rely on a previously issued unexecuted instruction for its resulting data or its implemented result. The CPU may also be capable of executing instructions speculatively, wherein conditional branch instructions may cause certain instructions to be fetched and issued based on a prediction of the condition. Therefore, depending on whether the CPU predicted correctly, the CPU will be either executing the correct instructions or not. Branch prediction and is relationship with speculative execution of instructions is well-known in the art. For a detailed explanation of speculative out-of-order execution, see M. Johnson, Superscalor Microprocessor Design, Prentice Hall, 1991. Speculative and out-of-order execution offer advantages over the prior art, including better use of resources.
However, memory operations typically must be executed in order to maintain memory consistency, especially when their execution would create incorrect results.
If multiple load operations may be executed at the same time, yet memory ordering still is being observed, the execution and retirement of memory operations must be managed. It is desirable to be able to manage the out-of-order execution and retirement of memory operations.
The present invention provides management for load operations that insures memory ordering while allowing multiple load operations to be retired at the same time.